There have been known liquid crystal display devices having optical sensors in picture elements or pixels (see Patent Literature 1 for example). A configuration of such a liquid crystal display device is explained with reference to FIG. 35.
FIG. 35 shows a configuration of an n-th row in a display region of a liquid crystal display panel. The configuration of the n-th row includes a plurality of picture elements PIX comparted by a gate line Gn, source lines S (in the drawing, Sm to Sm+3 are shown) and a retention capacitor line Csn, and at least one optical sensor circuit 102 connected with a reset line Vrstn and a read control line Vrwn. “n” and “m” at the end of a sign indicate a row number and a column number, respectively.
Each picture element PIX includes a TFT 101a serving as a selection element, a liquid crystal capacitor CL, and a retention capacitor CS. A gate of the TFT 101a is connected with the gate line Gn, a source of the TFT 101a is connected with the source line S, and a drain of the TFT 101a is connected with a picture element electrode 103. The liquid crystal capacitor CL is a capacitor formed by positioning a liquid crystal layer between the picture element electrode 103 and a common electrode Com. The retention capacitor CS is a capacitor formed by positioning an insulating film between the picture element electrode 103 or the drain electrode of the TFT 101a and the retention capacitor line Csn. Constant voltages for example are applied to the common electrode Com and the retention capacitor line Csn.
The optical sensor circuit 102 is provided in any number. For example, the optical sensor circuit 102 may be provided with respect to one picture element PIX or one pixel (e.g. a set of picture elements PIX corresponding to R, G, B, respectively). The optical sensor circuit 102 includes a TFT 102a, a photodiode 102b, and a capacitor 102c. A gate of the TFT 102a is connected with an electrode called a node net A, a drain of the TFT 102a is connected with one source line S (here, Sm), and a source of the TFT 102a is connected with another one source line S (here, Sm+1). An anode of the photodiode 102b is connected with the reset line Vrstn and a cathode of the photodiode 102b is connected with the node net A. One end of the capacitor 102c is connected with the node net A and the other end of the capacitor 102c is connected with the read control line Vrwn.
During a period other than a period in which a data signal is written into the picture element PIX, the optical sensor circuit 102 causes a voltage appearing at the node net A in accordance with intensity of light incident to the photodiode 102b to be outputted as a sensor output voltage Vom via the source of the TFT 102a so that the sensor output voltage Vom is outputted via the source line S connected with the source of the TFT 102a (this source line S serves as a sensor output line Vom when detecting light (for convenience of explanation, the sensor output line and the sensor output voltage are given the same reference sign)) to a sensor read circuit outside the display region. At that time, the TFT 102a serves as a source follower. Further, at that time, the source line S connected with the drain of the TFT 102a serves as a power source line Vsm to which a constant voltage is applied when light is detected. Alternatively, the sensor output line Vom and the power source line Vsm may be provided independently of the source lines S as shown by broken lines close to the source lines S.
With reference to FIG. 36, the following details the operation of the optical sensor circuit 102.
During a writing period in which a data signal is written, a gate pulse consisting of +24V High level and −16V Low level is outputted as a scanning signal to the gate line Gn, and data signals are outputted to the source lines S. A constant voltage (e.g. +4V) is applied to the retention capacitor line Csn. This operation is repeated with respect to picture elements PIX in each row per one vertical period (1V). Other than the writing period, the result of light detection by the optical sensor circuit 102 can be outputted to the sensor read circuit.
At a time (1), when a reset pulse Prstn consisting of −4V High level and −16V Low level for example is applied from an outside sensor drive circuit to the reset line Vrstn, the photodiode 102b gets conductive in a forward direction, and a voltage at the node netA is reset to a voltage at the reset line Vrstn. Thereafter, during a period (2), a leakage occurs in accordance with intensity of light incident to the photodiode 102b in a reverse biased state, so that the voltage at the node net A drops at a rate corresponding to the light intensity.
At a time (3), when a read pulse Prwn consisting of +24V High level and −10V Low level for example is applied from the sensor drive circuit to the read control line Vrwn, the voltage at the node netA increases. At that time, the voltage at the node netA goes beyond a threshold voltage of the TFT 102a. The sensor output voltage Vom outputted from the source of the TFT 102a while the read pulse Prwn is applied corresponds to the voltage at the node netA, i.e. corresponds to the light intensity. Accordingly, by the sensor read circuit reading the sensor output voltage Vom via the sensor output line Vom, it is possible to detect the light intensity. The optical sensor circuit 102 ends the output at a time (4), and stops its operation until next reset operation.